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Electronics & Communication Engineering

Electronics & Communication

VLSI Data Conversion Circuit

VLSI Data Conversion Circuit

01 Introduction to Data Conversion

04 Nonidealities in Samples

05 Noise due to Sampling

06 Distortion in a Sampling Switch

07 Gate Boosted Switches-1

08 Gate Boosted Switches-2

09 Charge Injection

10 S H Characterization-1

11 SH Characterization-2

12 FFTs and Leakage

13 Spectral Windows-1

14 Spectral Windows-2

15 ADC & DAC Definition

16 Quantization Noise-1

17 Quantization Noise-2

18 Over Sampling and Noise Shaping

19 Delta-Sigma Modulation-1

20 Delta-Sigma Modulation-2

21 Linearized Analysis

22 Stability of Delta Sigma Modulators

23 High Order DSMs

24 NTF Design and Tradeoffs

25 Single bit Modulators

26 Loop Filter Architectures

27 Continous-time Delta Sigma Modulation

28 Implicit Antialiasing

29 Modulators with NRZ and Impulsive DACs

30 High Order CTDSMs

32 Excess Loop Delay (ELD)

33 ELD Compensation

34 Effect of Clock Jitter on CTDSMs-1

35 Effect of Clock Jitter on CTDSMs-2

36 Dynamic Range Scaling

37 Simulation of CTDSMs

38 Integrator Design-1

39 Integrator Design-2

40 Flash ADC Design

41 Latches and Metastability

42 Offset in a Latch-1

43 Offset in a Latch-2 Auto Zeroing

44 Auto Zeroing-2

45 Auto Zeroing-3

46 Auto Zeroing in flash ADCs

47 Flash ADCs Case Study

49 Flash ADC in a Delta Sigma Loop

51 Binary and Themometer DACs

52 Segmented DACs

53 Optimal DAC Segmentation

54 DAC Nonlinearities

55 Current Steering DACs-1

56 Current Steering DACs-2

57 DAC Mismatches in DSMs

58 Calibration and Randomization

59 Dynamic Element 1

60 Dynamic Element 2

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